For reduction in power consumption demanded of SoC (System On a Chip) used in mobile phones, it is important to lower a supply voltage. However, with the scale-down of semiconductor processes, the leak current and process variations increase, and it is becoming difficult to lower the supply voltage. Under the circumstances, the AVS technique which enables each chip to be supplied with an optimum supply voltage depending on the process variation is in the spotlight. According to the AVS technique, the supply voltages are controlled so that the average gate delay variations of chips, namely the performances thereof, are uniform. For instance, in the case of a chip such that the process variation causes the gate delay to deviate from the center value to the faster or smaller side, the gate delay is corrected and shifted to the slower side by lowering the supply voltage. In contrast, in the case of a chip such that the process variation causes the gate delay to deviate from the center value to the slower or larger side, the gate delay is corrected and shifted to the faster side by raising the supply voltage. Applying an optimum supply voltage to each chip according to the process variation in this way, the reduction of power consumption can be achieved with no performance penalty. In addition to the correction of process variations, the AVS technique is applicable to the correction of gate delay variations caused by a temperature change, power-source noise in operation, and the aging of a device. In the light of the trend that the progress of scale-down of the future will enlarge the process variations, the AVS technique is regarded as indispensable. The detailed description of the AVS technique is presented by Mohamed Elgebaly et al., “Variation-Aware Adaptive Voltage Scaling System”, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 15, No. 5, May 2007, pp. 560-571.
In general, process variations are broadly classified into an inter-die or Global variation and an intra-die or Local variation according to the types. The inter-die variation is considered to be attributed to a temperature gradient on a wafer occurring in course of manufacture, a fabrication error owing to the variation of the optical path difference from a stepper to a wafer, arising in the process of lithography, or a systematic phenomenon like the dependence on a layout pattern. The inter-die variation has the feature that it changes gently in the surface of a wafer in quantity. In performing the adaptive voltage scaling on each chip, the supply voltage is controlled so that the mean value of gate delay of each chip is made constant, and then the inter-die variation is corrected on the assumption that the magnitude of the inter-die variation is substantially uniform in a chip. The inter-die variation is hereinafter referred to as “variability”.
On the other hand, the intra-die variation is considered to be attributed to an impurity density of a substrate varying in transistors. The intra-die variation has the feature that the intra-die variation of each transistor has no correlation to those of other transistors. In general, the probability distribution of the amount of gate delay can be expressed in the form of a normal distribution, and therefore, the magnitude of intra-die variation shall be expressed by a standard deviation. Now, the intra-die variation is hereinafter referred to as “uncertainty”. The descriptions about the variability and uncertainty are presented by Martin Eisele et al., “The Impact of intra-Die Device Parameter Variations on Path Delays and on the Design for Yield of Low Voltage Digital Circuits”, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 5, NO. 4, December 1997, pp. 360-368.
The types of process variations targeted for correction according to the AVS technique have been the variability primarily in the past. In such case, a system based on the AVS technique has, in outline, a sensor circuit provided in the chip thereof for measuring a mean value of gate delay, derives the variability from a result output by the sensor circuit, determines, from the value, the value of an optimum supply voltage, and applies the supply voltage to the chip. However, with the technique trend toward a finer structure, it is expected that the magnitude of uncertainty will be enlarged remarkably. Therefore, it is expected that the need to target the uncertainty for correction according to the AVS technique will increase. In this connection, Japanese Unexamined Patent Publication No. JP-A-2008-141013 describes an AVS technique arranged in consideration with both of variability and uncertainty, by which a chip has a plurality of sensor circuits provided therein for measuring a gate delay, and a calculating unit located outside the chip is used to determine the mean value and standard deviation of gate delay from output values of the sensor circuits.